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? semiconductor components industries, llc, 2002 july, 2002 rev. 2 1 publication order number: ncp5008/d ncp5008, ncp5009 backlight led boost driver the ncp5008/ncp5009 is a high efficiency boost converter operating in current loop control mode to drive light emitting diode. the current mode regulation allows a uniform brightness of the leds. features ? 2.7 to 6.0 v input voltage range ? output voltage from v bat to 15 v ? 3.0 a quiescent supply current ? automatically leds current matching ? no external sense resistor ? includes dimming function ? programmable or automatic current output mode ? local or remote control facility ? photo transistor sense feedback input ? inductor based converter brings high efficiency ? low noise dc/dc converter ? all pins are fully esd protected typical applications ? led display back light control ? high efficiency step up converter figure 1. typical battery powered led boost driver i ref photo l2 cs clk 1 2 q1 npnphoto gnd 4 v bat 3 5 6 local gnd 7 4 8 gnd l1 9 v bat 10 r1 30 k gnd microcontroller vcc gnd ncp5009 l1 22 h v bat c1 10 f/6.3 v gnd d5 mbr0520 led d1 led d2 led d3 led d4 2.2 f/16 v c2 gnd u1 vbias micro 10 dm suffix case 846b pin connections i ref v bat nc cs vbias l1 l2 iout gnd 110 2 3 4 9 8 7 10 1 5tx ayw marking diagram x = device number 8 or 9 a = assembly location y = year w = work week clock 5 local 6 i ref v bat photo cs vbias l1 l2 iout gnd 110 2 3 4 9 8 7 clock 5 local 6 ncp5008 ncp5009 see detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet. ordering information http://onsemi.com
ncp5008, ncp5009 http://onsemi.com 2 figure 2. block diagram back light white led current drive controller bandgap por por v bat v bat 10 r1 1r8 v bat isense 9 l1 a=10 + iout reference gnd v bat controller 8 l2 7 gnd iout q1 gnd bandgap reference v bat bandgap v bat _ok 2 photo (see note) 1 i ref 6 local v bat por 50 k q2 serial to parallel latches 1:8 v ref selection v ref 4 vbias 5 clk 3 cs note: this functionality is not implemented on the ncp5008 type. 50 k v bat gnd v bat v bat +
ncp5008, ncp5009 http://onsemi.com 3 pin function description pin symbol type description 1 i ref input this pin provides the output current range adjustment by means of a resistor connected to ground. the current output tolerance depends upon the accuracy of this resistor. using a 1% metal film resistor, or better, yields the best output current accuracy. 2 photo signal this pin provides an access to the output current control loop for the ncp5009 version. the current sunk to ground from this pin is subtracted from the output current mirror. primary use is the ambient light automatic adjustment by means of an external photo transistor connected across this pin and ground. the output current decreases as the ambient light increases. the internal circuit provides a 1/1 current ratio with the i ref defined by the resistor connected from pin 1 to ground. this current shall be limited to 65 a. this functionality is not implemented on the ncp5008 type. 3 cs input negative going chip select logic input. this pin is used to select the ncp5008/ ncp5009 and validate the clock/data when cs = low. the internal shift register is automatically clear to zero upon the falling edge, thanks to a 20 ns builtin one shoot. the builtin pullup resistor disables the device when the cs pin is left open. 4 vbias power this pin should be connected to v bat . 5 clock input the clock signal connected to this pin is used to serially shift right the internal preset high logic level. the clock is valid between the falling edge and until the rising edge of the cs . there is neither a feedback nor an overflow control. if the clock count exceeds 8 bits, the internal register is clear, the output current is forced to zero and the device comes back to the shutdown mode. 6 local input this pin is used to select the mode of operation. ? when local = high or open, the chip is controlled by two digital lines: cs and clock. the output current is programmed by the logic control of these pins, allowing a current adjustment within the range defined by the i ref resistor. ? when local = low, the chip is turned on /off by means of the cs line, the clock pins being deactivated. the output current is constant, as defined by the i ref resistor value. in order to minimize the standby current a dynamic pullup resistor is activated when por is high, this pullup resistor being disconnected when local = low. 7 gnd power this pin is the system ground for the ncp5008/ncp5009 and carries both the power and the digital signals. high quality ground must be provided to avoid spikes and/or uncontrolled operation. care must be observed to avoid highdensity current flow in a limited pcb copper track. 8 l2 power this pin is the power side of the external inductor and must be connected either to the external schottky diode (see figure 22) or directly to one external led (see figure 23). it provides the output current to the load. since the boost converter operates in a current loop mode, the output voltage can range up to +15 v but shall not extend this limit. the user must make sure this voltage will not be exceeded during the normal operation of this part. an external low cost ceramic capacitor (2.2 f/16 v, esr < 100 m w ) is recommended to smooth the current flowing into the diode(s), thus limiting the noise created by the fast transients present in this circuitry. care must be observed to avoid emi though the pcb copper tracks connected to this pin. 9 l1 power the return side of the external inductor shall be connected to this pin. typical application will use a 22 h, size 1210, to handle the 2.8 to 364 ma max range. on the other hand, when the desired output current is above 20 ma, the inductor shall have an esr < 1.0 w . the output current tolerance can be improved by using a larger inductor value. 10 v bat power the external voltage supply is connected to this pin. a high quality reservoir capacitor must be connected across pin 10 and ground to achieve the specified output voltage parameters. a 10 f/6.3 v, low esr capacitor must be connected as close as possible across pin 10 and ground pin 7. the x5r ceramic types are recommended.
ncp5008, ncp5009 http://onsemi.com 4 table 1. shift register bits assignment and functions setreg shift register (note: the register content is latched upon cs positive going). b7 b6 b5 b4 b3 b2 b1 bn value after por 0 0 0 0 0 0 0 iout peak (ma) i ref *k*7.5 i ref *k*6.5 i ref *k*5.5 i ref *k*4.5 i ref *k*3.5 i ref *k*2.5 i ref *k*1.5 local clock cs b1b7 output peak current l x h x 0 l x l x i ref * k * 7.5 h or open x h no change i ref * k * (bn + 0.5) h or open l no change i ref * k * (bn + 0.5) h or open l q data bn i ref * k * (bn + 0.5) the register is clear to zero during the first 20 ns following the cs falling edge. note: coefficient value (internal ratio): k = 746 maximum output peak current @ b7 = 1 and iphoto = 0 a : iout peak = i ref * (7 + 0.5) * 746 = i ref * 5595 i ref v ref r1 1.24 v r1
ncp5008, ncp5009 http://onsemi.com 5 maximum ratings rating symbol value unit power supply v bat , v bias 7.0 v output power supply voltage compliance v l2 16 v digital input v oltage digital input current clk, cs 0.3 v v bat + 3.0 v 1.0 v ma human body model: r = 1500 w , c = 100 pf esd 2.0 kv machine model esd 200 v micro 10 package power dissipation @ t a = +85 c thermal resistance junctiontoair p d r thja 200 200 mw c/w operating ambient temperature range t a 25 to +85 c operating junction temperature range t j 25 to +125 c maximum junction t emperature t jmax +150 c storage temperature range t stg 65 to +150 c maximum ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolute maximumrated conditions is not implied. functional operation should be restricted to the rec ommended operating conditions. power supply section (25 c to +85 c ambient temperature, unless otherwise noted.) rating pin symbol min typ max unit power supply 10 v bat 2.7 6.0 v power supply threshold start up voltage 10 v batthr 2.3 2.7 v output load voltage compliance 8 v out 15.0 v pulsed current regulation range 8 i out 0 400 ma continuous dc current in the load 8 i out 75 ma output pulsed current tolerance @ v bat = 3.6 v, l1 = 22 h/0.71 w, r ref 1%, i led = 20 ma (note 1) 8 i out 5.0 % output leakage @ local = 0, cs = h, vout = 15 v, v bat = 6.0 v 8 i out 500 na standby current @ iout = 0 ma, cs = h, clk = h, v bat = v bias = 3.6 v 10 i stdb 3.0 a standby current @ iout = 0 ma, cs = h, clk = h, v bat = v bias = 6.0 v 10 i stdb 10 a operating current @ v bat = v bias = 3.6 v, i ref = 30 a, clk = h, cs = l, local = open 10 i ope 600 a boost internal oscillator clock @ l1 = 22 h, v bat = v bias = 3.6 v, iout = 20 ma (vout = 14 v) f osc 300 khz 1. the tolerance refers to the 20 ma to 70 ma current range.
ncp5008, ncp5009 http://onsemi.com 6 digital section (25 c to +85 c ambient temperature, unless otherwise noted.) rating pin symbol min typ max unit high level input v oltage low level input v oltage input capacitance 3, 5 v ih v il c in 0.7 * v bat 10 v bat 0.3 * v bat v v pf high level input v oltage low level input v oltage input capacitance 6 v ih v il c in 0.6 * v bat 0.4 * v bat 10 v v pf local pullup resistor 6 r loc 20 80 k w local leakage current 9 i loc 100 na cs pullup resistor 3 r cs 20 80 k w minimum cs low time 3 tc s setup 250 ns clock frequency 5 f clk 5.0 mhz clock tr and tf 5 tr clk , tf clk 10 ns internal register clear t clear 10 30 ns internal power on reset width t por 100 s 2. digital inputs undershoot < 0.30 v, digital inputs overshoot < 0.30 v. analog section (25 c to +85 c ambient temperature, unless otherwise noted.) rating pin symbol min typ max unit output voltage range reference @ 2.5 a < i ref < 65 a (note 3) 1 v ref 1.20 1.24 1.28 v maximum output current range ratio 8 i out 5595 minimum output current range ratio 8 i out 1119 output current sense resistor 10, 9 r s 1.8 2.2 w output voltage range reference @ 2.5 a < ipho < 65 a 2 v pho 1.20 1.24 1.28 v output current stabilization tdelay following a dc/dc start up 8 i outdly 100 s internal nmos resistor @ v bat = 3.6 v 8 qr dson 2.2 3.0 w internal comparator delay time td comp 60 ns 3. the overall tolerance depends upon the accuracy of the external resistor. using a 1%/low ppm metal film resistor is recommend ed to achieve 5% output current tolerance.
ncp5008, ncp5009 http://onsemi.com 7 50 55 60 65 70 75 80 0 5 10 15 20 25 30 35 efficiency (%) figure 3. efficiency vs. load current @ 4 leds (v load = 4*vf ? 14.2 v ) figure 4. efficiency vs. load current @ 3 leds (v load = 3*vf ? 10.5 v ) figure 5. efficiency vs. load current @ 2 leds (v load = 2*vf ? 7.1 v) 60 65 70 75 80 85 0 5 10 15 20 25 30 35 figure 6. efficiency vs. v bat @ v out = 15 v/i led = 20ma and v out = 7.5 v/i led = 40 ma figure 7. efficiency vs. load current @ 4 leds (v load = 2 strings of 2 leds in series = 7.1v) figure 8. inductor peak current vs. i ref @ bn = {1, 2, 3, 4, 5, 6, 7} 0 50 100 150 200 250 300 350 400 0 20406080 i ref ( a) v bat = 3.6 v v bat = 4.2 v v bat = 3.0 v i led (ma) 50 55 60 65 70 75 80 0 5 10 15 20 25 30 35 efficiency (%) i led (ma) efficiency (%) i led (ma) 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 efficiency (%) v bat (v) 6.5 v out =7.5 v i led = 40 ma v out = 15 v i led = 20 ma 100 0 102030 4050 6070 efficiency (%) i led (ma) i peak (ma) v bat = 6.0 v 3.0 v 3.6 v 4.2 v 5.0 v bn 7 4 3 2 1 6 5 v bat = 3.6 v v bat = 4.2 v v bat = 3.0 v v bat = 3.6 v v bat = 4.2 v v bat = 3.0 v 90 80 70 60 50 95 90 85 80 75 typical operating characteristics condition: typical application: l = 22 h, cin = 10 f, cout = 2.2 f, r1 = 30 k
ncp5008, ncp5009 http://onsemi.com 8 figure 9. load current (i led ) vs. i ref @ v bat = 3.6 v, v load = 15 v and 10 v 0 5 10 15 20 25 30 35 40 45 50 0 10 20304050 6070 i ref ( a) figure 10. inductor peak current error vs. theoretical inductor peak current 0 2 4 6 8 10 12 14 16 18 20 0 50 100 150 200 250 300 350 40 0 figure 11. inductor peak current vs. i photo @ i ref = 34 a 0 20 40 60 80 100 120 140 160 180 200 0 1020 3040 figure 12. stand by current vs. v bat @ t = 20 c 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 i led (ma) v load = 10 v v load = 15 v i photo ( a) i peak (ma) theoretical i peak (ma) i peak error (%) v bat (v) 6.0 typical operating characteristics condition: typical application: l = 22 h, cin = 10 f, cout = 2.2 f, r1 = 30 k theoretical measured i stby ( a)
ncp5008, ncp5009 http://onsemi.com 9 70 75 80 85 90 95 100 01020304050607 0 efficiency (%) v bat = 6.0 v i led (ma) 60 65 70 75 80 85 90 0 5 10 15 20 25 30 35 efficiency (%) i led (ma) 50 55 60 65 70 75 80 0 5 10 15 20 25 30 3 5 efficiency (%) i led (ma) 85 figure 13. efficiency vs. load current @ 4 leds (v load = 4*vf ? 14.2 v ) figure 14. efficiency vs. load current @ 3 leds (v load = 3*vf ? 10.5 v ) figure 15. efficiency vs load current @ 2 leds (v load = 2*vf ? 7.1 v) figure 16. efficiency vs load current @ 4 leds (v load = 2 strings of 2 leds in series = 7.1 v) 50 55 60 65 70 75 80 0 5 10 15 20 25 30 35 efficiency (%) v bat = 3.6 v v bat = 4.2 v v bat = 3.0 v i led (ma) 5.0 v 4.2 v 3.6 v 3.0 v v bat = 3.6 v v bat = 4.2 v v bat = 3.0 v v bat = 3.6 v v bat = 4.2 v v bat = 3.0 v typical operating characteristics condition: typical application: l = 22 h, cin = 10 f, cout = 2.2 f, r1 = 30 k
ncp5008, ncp5009 http://onsemi.com 10 operating description figure 17. digital timing definitions 90% 50% 10% t clkmin tf tr figure 18. typical schmitt trigger characteristic v bat on off output 0.30* v bat 0.70* v bat v bat input input schmitt triggers all the logic input pins have builtin schmitt trigger circuits to prevent the ncp5008/ncp5009 against uncontrolled operation. the typical dynamic characteristics of the related pins are depicted in figure 18. the output signal is guaranteed to go high when the input voltage is above 0.70*v bat , and will go low when the input voltage is below 0.30*v bat . esd protection the ncp5008/ncp5009 includes silicon devices to protect the pins against the esd spikes voltages. to cope with the different esd voltages developed in the applications, the builtin structures have been designed to handle 2.0 kv in human body model (hbm) and 200 v in machine model (mm) and on each pin.
ncp5008, ncp5009 http://onsemi.com 11 programming sequence figure 19. programming sequence i out ref iout b7 b6 b5 b4 b3 b2 b1 qdata clk clear cs tcssetup tclear last latched bit output current programmed register internal latch data and reset ioutdly upon cs transition from high to low, the internal sequence will take place: qdata is internally set to high level. upon positive going transition of the next clk signal, the qdata is shifted to the next bn stage. clear the qdata flipflop upon the positive going of the setreg[b1] transient. the sequence keeps going until cs = high. when the cs line returns to a high state, the programming output current flipflop is set according to the previous state of the shift register and setreg b[17] is cleared afterward. depending upon the cs width, for a given clk period, the last setreg bit will be latched and the output current will be adjusted accordingly. if the number of clk pulses is higher than 7, the qdata is lost and the setreg register bits b[17] are in the low state, yielding a zero output current. the internal shift register can be clear by sending more than 7 pulses to the clk pin when the pin cs is low. if the internal shift register is clear upon the cs transition from low to high, the device will be placed or maintained in the shut down mode. when the register content is higher than zero, the dc/dc is activated and a 100 s delay (typical) is necessary to stabilize the output current to the programmed value.
ncp5008, ncp5009 http://onsemi.com 12 set up output current range figure 20. functional diagram v bat + - 1 1 v bat bandgap gnd i ref gnd v bat + - 1 1 v bat bandgap gnd photo q1 npnphoto gnd gnd gnd 1:bn gnd gnd 1 gnd 2:1 v bat 1 1:746 i = (i ref iphoto)*(bn+0.5) iout reference = (i ref iphoto)*746*(bn+0.5) r ref 30 k i ref iphoto 1 1 the current sunk to ground on photo pin is subtracted from the current sunk to ground on i ref pin. the result is multiplied by the programmed value (bn) and then multiplied by the constant factor ratio (k = 746) in the current mirror. the constant factor k is a ratio between the current on iout sense and the iout reference internally fixed. the output current reference is: ipeak = ivalley + (i ref iphoto) * bn * k. where k = 746, bn represents the bit of the internal shift register, range from 1 to 7, and ivalley = (i ref iphoto) * 0.5 * k. we can write also ipeak = (i ref iphoto) * (bn + 0.5) * k. please find below the formula to quickly calculate r1 resistor (resistor on i ref pin): i ref 1.24 r1
ncp5008, ncp5009 http://onsemi.com 13 dc/dc converter operation the dc/dc converter operates with a boost structure depicted in figure 21, the load being supplied by the pulsed current coming from the external inductor l1. the current is monitored by the internal sense resistor rsense to set and reset the flipflop u3 and u6 according to the comparators u2 and u4 output state. figure 21. basic dc/dc boost structure + - + - v bat gnd u1 rsense 1r8 v bat l1 v bat l1 22 h l2 q1 gnd v bat gnd i peak_ref i valley_ref v bat + - u2 u4 gnd por u5 d4 led d3 led d2 led d1 led d5 mbr0520 gnd gnd c2 2.2 f/16 v u7 u3 u6
ncp5008, ncp5009 http://onsemi.com 14 output load drive in order to make profit of the builtin boost capabilities, one shall operate the ncp5008/ncp5009 in the continuous output current mode. such a mode is achieved by using and external reservoir capacitor (preferably a low esr ceramic type) across the led as depicted in figures 22, 23, 24, 25, and 26. using an extra photo sensor is not mandatory and the related pin 2 can be either left open or connected to v bat , but must not be grounded on the ncp5009 version only. at this point, the designer must carefully analyze two parameters: 1. the output voltage must be limited to 15 v maximum. it's the designer responsibility to make sure that spike voltages beyond the maximum rating will not exist across pin 8 and ground. depending upon a specific application (v bat voltage, pcb layout ), using an external voltage clamp could be necessary. 2. the peak current flowing into the led diodes shall be within the maximum ratings specified for these devices. the schottky diode d5, associated with capacitor c2, provides a rectification and filtering function. when a pulseoperating mode is acceptable: ? the leds brightness can be controlled in local mode with a pwm on cs pin as depicted in figure 24. ? or the schottky can be removed and replaced by at least one led diode as depicted in figure 23. typical application circuit figure 22. basic dc current mode operation in remote control i ref photo l2 cs clk 1 2 q1 npnphoto gnd 4 v bat 3 5 6 local gnd 7 4 8 gnd l1 9 v bat 10 r1 30 k gnd microcontroller vcc gnd ncp5009 l1 22 h v bat c1 10 f/6.3 v gnd d5 mbr0520 led d1 led d2 led d3 led d4 2.2 f/16 v c2 gnd u1 vbias
ncp5008, ncp5009 http://onsemi.com 15 figure 23. typical semipulsed mode of operation in remote mode i ref photo l2 cs clk 1 2 q1 npnphoto gnd 4 v bat 3 5 6 local gnd 7 4 8 gnd l1 9 v bat 10 r1 30 k gnd microcontroller vcc gnd ncp5009 l1 22 h v bat c1 10 f/6.3 v gnd led d3 led d4 1.0 f/16 v c2 gnd u1 vbias figure 24. pwm current control mode operation in local mode i ref photo l2 cs clk 1 2 q1 npnphoto gnd 4 v bat 3 5 6 local gnd 7 4 8 l1 9 v bat 10 r1 30 k gnd ncp5009 l1 22 h v bat c1 10 f/6.3 v gnd d5 mbr0520 led d1 led d2 led d3 led d4 2.2 f/16 v c2 gnd u1 vbias pwm gnd
ncp5008, ncp5009 http://onsemi.com 16 figure 25. dac current control mode operation in local mode i ref photo l2 cs clk 1 2 q1 npnphoto gnd 4 v bat 3 5 6 local gnd 7 4 8 l1 9 v bat 10 r1 30 k ncp5009 l1 22 h v bat d5 mbr0520 led d1 led d2 led d3 led d4 2.2 f/16 v c2 gnd u1 vbias gnd dac off on c1 10 f/6.3 v gnd figure 26. basic dc current mode operation in local mode i ref photo l2 cs clk 1 2 q1 npnphoto gnd 4 v bat 3 5 6 local gnd 7 4 8 l1 9 v bat 10 r1 30 k ncp5009 l1 22 h v bat d5 mbr0520 led d1 led d2 led d3 led d4 2.2 f/16 v c2 gnd u1 vbias gnd off on c1 10 f/6.3 v gnd gnd
ncp5008, ncp5009 http://onsemi.com 17 typical leds load mapping figure 27. three different examples of load can be driven by the ncp5009 or ncp5008 condition: v bat = 3.6 v, l = 22 h d1 led gnd d2 led d3 led d4 led d5 led d6 led d7 led d8 led d9 led d10 led load+ 75 ma 6.7 v example 1 d1 led d2 led d3 led d4 led d5 led d6 led load+ 60 ma 6.7 v example 2 d1 led d2 led load+ 50 ma 10.4 v example 3 d3 led d4 led d5 led d6 led d7 led d8 led d9 led gnd gnd manufacturer reference design ref value/reference or size manufacturer ref # d5 mbr0520/sod123 on semiconductor mbr0520 l1 22 h/1210 murata lqh3c220k34 c1 10 f/ 6.3 v/0805 murata grm40 x5r 106k 6.3 c2 2.2 f/16 v/1206 murata grm426 x7r 225k 16 q1 sfh320/plcc2 osram sfh320 d1 to d4 white led osram lw5413vbw1
ncp5008, ncp5009 http://onsemi.com 18 ordering information device operating t emperature range package shipping marking ncp5008dmr2 25 c top +85 c micro 10 4000 tape and reel 5t8 ncp5009dmr2 25 c top +85 c micro 10 4000 tape and reel 5t9 layout example figure 28. typical printed circuit layout (the top silk screen and the top layer) the figure 28 represents the typical printed circuit layout based on the basic application figure 1. this application has been routed on a single copper layer to save cost. a dual side pcb has better noise protection and can be the right choice for an industrial system. in order to avoid voltage spikes, care must be observed to group the capacitors, the inductor, the schottky diode and the integrated circuit in the same area. on the other hand, using large copper tracks to reduce the resistor connectivity is strongly recommended. obviously, the connectors gnd, clk, cs , v bat and load are for engineering purpose only and not for final application.
ncp5008, ncp5009 http://onsemi.com 19 package dimensions micro 10 dm suffix case 846b02 issue b s b m 0.08 (0.003) a s t dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c 0.95 1.10 0.037 0.043 d 0.20 0.35 0.008 0.014 g 0.50 bsc 0.020 bsc h 0.05 0.15 0.002 0.006 j 0.10 0.21 0.004 0.008 k 4.75 5.05 0.187 0.199 l 0.40 0.70 0.016 0.028 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a" does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b" does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. 846b-01 obsolete. new standard 846b-02 b a d k g pin 1 id 8 pl 0.038 (0.0015) t seating plane c h j l
ncp5008, ncp5009 http://onsemi.com 20 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provid ed in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into t he body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ncp5008/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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